1. Technical Field of the Invention
This invention is related to a method and apparatus for adaptive signal encoding schemes based on the capacitive coupling effects. The coupling effects include coupling capacitances between adjacent signal lines as well as coupling effects between signal lines and a metal layer. The invention does not assume any a priori knowledge that is particular to a specific set of signals traversing the signal lines.
2. Description of the Related Art
The following references provide useful background information on the indicated topics, all of which relate to the invention, and are incorporated herein by reference:
International Technology Roadmap for Semiconductors, 1999 Edition, http://www.semichips.org/news/events/itrs99/, downloaded and printed on Feb. 13, 2001;
Farid N. Najm, Transition Density: A New Measure of Activity in Digital Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 2, pp. 310-323, (February 1993);
Milind B. Kamble and Kanad Ghose, Analytical Energy Dissipation Models For Low Power Caches, IEEE Proceedings of Symposium on Low Power Electronics and Design, pp. 143-148 (1997);
Kiyoo Itoh, Katsuro Sasaki and Yoshinobu Nakagome, Trends in Low-Power RAM Circuit Technologies, Proceedings of the IEEE, Vol. 83, No. 4, pp. 524-543 (April 1995);
Tony Givargis, Frank Vahid and Jxc3x6rg Henkel, Fast Cache and Bus Power Estimation for Parameterized System-On-A-Chip Design, Proceedings of IEEE/ACM Conference on Design Automation and Test in Europe (DATE00) (March 2000);
Ricardo Gonzales and Mark Horowitz, Energy Dissipation in General Purpose Processors, IEEE Proceedings of Symposium on Low Power Electronics, pp. 12-13 (1995);
V. Tiwari, Logic and System Design for Low Power Consumption, Ph.D. thesis, Princeton University, November 1996;
Mircea R. Stan and Wayne P. Burleson, Bus-Invert Coding for Low-Power I/O, IEEE Transactions on VLSI Systems, Vol. 3, No. 1, pp. 49-58 (March 1995);
Preeti R. Panda and Nikil D. Dutt, Low-Power Memory Mapping Through Reducing Address Bus Activity, IEEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 309-320 (September 1999);
Paul P. Sotiriadis and Anantha Chandrakasan, Low Power Bus Coding Techniques Considering Inter-wire Capacitances, Proceedings of IEEE Conference on Custom Integrated Circuits, pp. 507-510 (2000);
Ki-Wook Kim, Kwang-Hyun Baek, Naresh Shanbhag, C. L. Liu and Sung-Mo Kang, Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design, Proceedings of IEEE 37th Design Automation Conference, pp. 318-321 (2000);
L. Benini, A. Macii, E. Macii, M. Poncino and R. Scarsi, Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses, Proceedings of IEEE 36th Design Automation Conference, pp. 128-133 (1999);
Huzefa Mehta, Robert M. Owens and Mary J. Irwin, Some Issues In Gray Code Addressing, Proceedings of IEEE Conference, 6th Great Lakes Symposium on VLSI, pp. 178-181 (1996);
Ching-Long Su, Chi-Ying Tsui, and Alvin Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design and Test Magazine, Vol. 11, No. 4, pp. 24-31 (Winter 1994);
Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto and Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of IEEE Conference, 7th Great Lakes Symposium on VLSI, pp. 77-82 (1997);
Enric Musoll, Tomxc3xa1s Lang and Jordi Cortadella, Working-Zone Encoding for Reducing the Energy in Microprocessor Address Buses, IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 568-572 (December 1998);
William Fornaciari, Donatella Sciuto and Cristina Silvano, Power Estimation for Architectural Exploration of HW/SW Communication on System-Level Buses, Proceedings of IEEE International Workshop on HW/SW Co-Design, pp. 152-156 (1999);
Andrea Acquaviva and Riccardo Scarsi, A Spatially-Adaptive Bus-Interface for Low-Switching Communication, Proceedings of IEEE International Symposium on Low Power Electronics and Design, pp. 238-240 (2000);
Sumant Ramprasad, Naresh Shanbhag and Ibrahim N. Hajj, A Coding Framework for Low-Power Address and Data Buses, IEEE Transactions on VLSI Systems, Vol. 7, No. 2, pp. 212-221 (June 1999);
Yan Zhang, Wu Ye and Mary J. Irwin, An Alternative Architecture For On-Chip Global Interconnect: Segmented Bus Power Modeling, Conference Record (Signals, Systems and Computers) of 32nd Asilomar Conference, pp. 1062-1065 (1998); and
Mircea R. Stan and Wayne P. Burleson, Low-Power Encodings for Global Communication in CMOS VLSI, IEEE Transactions on VLSI Systems, Vol. 5, No. 4, pp. 444-455 (December 1997).
There will now be provided a discussion of various topics to provide a proper foundation for understanding the invention.
Minimizing power consumption of digital systems has become a crucial task. From a technology point of view, high power and/or energy consumption can cause integrated circuits to overheat, resulting in an acceleration of electro-migration processes and other undesirable effects. An integrated circuit with a high consumption of energy will likely malfunction.
From an application point of view, the power/energy consumption of a system is crucial. For example, consider mobile computing devices: if the power/energy consumption is low, operational time between recharges is extended. This extended operational time allows the implementation of additional functionality that previously could not be added due to energy constraints (e.g., a battery""s limited amount of energy).
Many consumer devices are designed as a Systems-On-a-Chip (SOC) that comprise multiple system components (e.g., CPU, MPEG decoder, etc.) on a single silicon substrate. As SOC functionality and complexity increases, so does the communication infrastructure necessary for efficient (i.e., fast) information exchange information between those components. As a result, the amount of energy that the SOC communications infrastructure (e.g., signal groups, bus lines, etc.) consumes has a significant impact.
The trend towards deep sub-micron designs of 0.18 microns or less also contributes to the increasing impact of power/energy consumption of the communication infrastructure. Effects that could be neglected in the past are now becoming increasingly important. One effect is the coupling capacitance that exists between physically close signal lines. The spatial closeness of signal lines increases the wire-to-wire capacitance such that it may exceed the base capacitance of a wire, i.e., the wire-to-metal-layer capacitance. In this context, a xe2x80x9cmetal layerxe2x80x9d is a layer on integrated circuit layout having a zero voltage potential.
For CMOS circuits, it is implicitly assumed that power consumption is due to switching activity only. Leakage currents, however, might become a larger source of power consumption in the future. At present, switching activity in CMOS is the primary source of power consumption.
With these coupling effects in mind, the number of switching activities of a group of signals (e.g., a series of transitions on a group of address bus lines) does not necessarily reflect the power that is consumed by the group of signals. As noted by Najm, this is true for non-deep sub-micron designs. In this context, a non-deep sub-micron design is a design wherein the spatial proximity of signal lines or devices does not lead to coupling capacitances that are in the same order of magnitude as the intrinsic (i.e., base) capacitances. Hence, encoding mechanisms for reducing signal line power consumption that rely solely on minimizing the number of transitions are not efficient any more. In fact, any efficient encoding scheme for deep sub-micron signal lines should be based on a precise physical signal line model.
Power modeling/optimization of SOCs has been addressed at various levels of abstraction, as well as for various system components. Kamble et al. discuss analytical models for estimating the energy dissipation of conventional caches and low power caches. Itoh et al. disclose energy conservation for dynamic and static random access memory components. Givargis et al. disclose techniques for estimating power consumption of caches and bus subsystems within a SOC. Gonzales and Horowitz discuss how pipelining affects the energy-delay product inside general-purpose processors. This list is exemplary in nature, and is given only to present an overview of power optimization efforts in other areas of integrated circuit design.
Early work on minimizing the transition activities on input/output buses has been conducted by Stan and Burleson. The idea is to transmit the inverted word through the input/output bus when the Hamming Distance (HD) of the non-inverted word would result in HD greater than N/2 with N being the number of input/output bus lines. This approach requires minimal additional logic, plus one control bus line that signals whether or not the invert mode is being applied for a particular transition. Panda et al. approach the problem of reducing switching activities of address busses by exploiting the characteristics of accesses to memory arrays. Various scenarios for memory mapping schemes due to different memory organizations were investigated.
Benini et al. present an adaptive approach for encoding signals that are transmitted through wide and heavily loaded buses. The approach uses algorithms to synthesize encoding and decoding logic that minimizes the average number of transitions on a heavily loaded bus.
Panda et al., Metha et al. and Su et al. have studied the exploitation of correlated access patterns (e.g., address buses) by using Gray Code encoding. Benini et al. have improved upon Gray Code using a methodology that benefits from the fact that a fairly high number of patterns in address buses are consecutive. Then, the receiving side of an address bus can calculate the address without the necessity to actually having the address code being transmitted via the address bus.
Musoll et al. have proposed a working zone encoding scheme to reduce the energy consumed by microprocessor buses. The encoding is adjusted to where, within an address word, the switching activity is actually taking place. Acquaviva et al. have presented a synthesis method for a spatially adaptive bus interface that does not need any a priori knowledge of the data being transferred.
Ramprasad et al. present a framework to study various encoding schemes for address and data buses that can be applied to high-capacitance buses. Zhang et al. provide an approach of segmenting a bus and thereby exploit the effect of having smaller effective bus capacitances that apply during bus transitions. Fornaciari et al. have investigated power consumption of buses from a system-level point of view and they quantify the effect of cache sizes and other parameters for different encoding methods. Another system-level oriented approach for communication architectures is presented by Stan et al., focusing on low power encoding techniques under specific consideration of influences on possible area and performance impacts.
The approach of Sotiriadis et al. takes into consideration the capacitances between signal lines, than just the wire-to-metal-layer capacitance. They use a static encoding technique to achieve power savings. Kim et al. introduce a coupling-sensitive invert scheme that also provides power savings.
The reduction of transition activity (i.e., the number of low/high, high/low transitions) does not necessarily lead to lower power consumption in deep sub-micron designs. The characteristics of deep sub-micron signal lines and the exploitation of these characteristics are just starting considered by designers, and designs with those characteristics (i.e., signal line-to-signal line capacitances are in the same order of magnitude as signal line-to-metal layer capacitances) will be commercially exploited in the near future. As opposed to the approaches of Sotiriadis et al. and Kim et al., the present invention is adaptive in nature and can exploit characteristics on the signal lines that are changing over time. In addition, the present invention quantifies the capacitances through the signal line capacitance model and the encoding schemes are adjusted to this model. The present invention uses a signal line capacitance model that reflects signal line-to-signal line capacitances in conjunction with an adaptive encoding scheme. The present invention improves power consumption as compared to Gray Code encoding which is accepted as the benchmark-encoding scheme for address buses.
The present invention has been made in view of the above circumstances and to overcome the above problems and limitations of the prior art.
Additional aspects and advantages of the present invention will be set forth in part in the description that follows and in part will be obvious from the description, or may be learned by practice of the present invention. The aspects and advantages of the present invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
A first aspect of the present invention provides an encoding method for a plurality of closely spaced electrical signal paths, the encoding method comprising determining signal transition activity for each electrical signal path for a predetermined set of electrical impulses. For example, object code that is executing can be considered as a predetermined set of electrical impulses that transition across the plurality of closely spaced electrical signal paths. The encoding method further provides for the grouping the electrical signal paths into a plurality of source windows, and each source window comprises a portion of the electrical signal paths and each portion comprising adjacent electrical signal paths. The encoding method further provides cross-connecting the source windows to a plurality of target windows based upon a base capacitance between each of the electrical signal paths and a ground plane layer, a coupling capacitance between each of the electrical signal paths and the signal transition activity.
The encoding method further provides for the cross-connecting of source windows to target windows, by arranging the connections between the plurality of source windows and the plurality of target windows such that target windows having electrical signal paths with low signal transition activity are interposed between target windows having high signal transition activity. The encoding method further provides for the cross-connection of source windows to target windows by arranging the connections between the plurality of source windows and the plurality of target windows such that the two target windows having electrical signal paths with highest signal transition activity are separated by the remaining target windows.
A second aspect of the present invention provides an encoding method for a plurality of closely spaced electrical signal paths, the encoding method comprising determining signal transition activity for each electrical signal path for a given set of electrical impulses. For example, object code that is executing can be considered as a predetermined set of electrical impulses that transition across the plurality of closely spaced electrical signal paths. The encoding method further provides dividing the electrical signal paths into a number of windows such that W=P/WS, wherein each window comprises a number of adjacent electrical signal paths, and W represents the number of windows, P represents the number of electrical signal paths, and WS represents the number of electrical signal paths in a window. The encoding method further provides arranging the windows such that windows having electrical signal paths with a large amount of signal transition history are separated by windows having electrical signal paths with a low amount of signal transition history.
A third aspect of the present invention provides an encoding method for a plurality of closely spaced electrical signal paths, the encoding method comprising determining a signal transition history for each electrical signal path for a given set of electrical impulses, and dividing the electrical signal paths into a number of windows such that W=P/WS. Each window comprises a number of adjacent electrical signal paths, and W represents the number of window, P represents the number of electrical signal paths, and WS represents the number of electrical signal paths in a window. The encoding method further provides for arranging the windows such that the two windows having electrical signal paths with the largest amount of signal transition history are separated by the remaining windows.
A fourth aspect of the present invention provides an encoding method for a plurality of closely spaced electrical signal paths, wherein a predetermined set of synchronous electrical impulses traverse the electrical signal paths, the encoding method comprising determining a signal transition history for each electrical signal path for the predetermined set of synchronous electrical impulses, and dividing the electrical signal paths into a number of windows such that W=P/WS. Each window comprises a number of adjacent electrical signal paths, and W represents the number of window, P represents the number of electrical signal paths, and WS represents the number of electrical signal paths in a window. The encoding method further provides arranging the windows such that the two windows having electrical signal paths with the largest amount of signal transition history are separated by the remaining windows, analyzing the signal transitions within each window, and if a majority of the windows contain a large amount of transition activity, inverting the synchronous electrical impulses.
A fifth aspect of the present invention provides an encoding method for an address bus, wherein a given set of synchronous address bit signals traverse the address bus, the encoding method comprises determining a signal transition history for each address bit on the address bus. The encoding method further provides dividing the address bus into a number of windows such that W=P/WS. W represents the number of windows, P represents the number of bits in the address bus, and WS represents the number of address bus bits in a window. The encoding method further provides arranging the windows such that the two windows having address bus bits with the largest amount of signal transition history are separated by the remaining windows, and analyzing the address bus signal transitions within each window. If a majority of the windows contain a large amount of transition activity, the address bit signals traversing the address bus are inverted.
A sixth aspect of the present invention provides an encoding method for an address bus, wherein a given set of synchronous address bit signals traverse the address bus, the encoding method comprises determining a signal transition history for each address bit on the address bus, and dividing the address bus into a number of windows such that W=P/WS. W represents the number of windows, P represents the number of bits in the address bus, and WS represents the number of address bus bits in a window. The encoding method further provides arranging the windows such that windows having address bits with a large amount of signal transition history are separated by windows having address bits with a low amount of signal transition history, and analyzing the address bus signal transitions within each window. If a majority of the windows contain a large amount of transition activity, the address bit signals traversing the address bus are inverted.
A seventh aspect of the present invention provides a signal encoding apparatus for a plurality of closely spaced signal lines, comprising a plurality of encoders connected to the plurality of closely spaced signal lines, a first multiplexer connected to the plurality of encoders to selectively switch between the output of each encoder, and an extended transition activity measurement circuit connected to the first multiplexer. The apparatus further provides a first signal inverter connected to the extended transition activity measurement circuit, and a first comparator to connected to the multiplexer, the comparator transmitting a signal to switch the multiplexer between the encoders.
The signal encoding apparatus further comprises a second signal inverter, a plurality of decoders connected to the second signal inverter, and a second multiplexer connected to the plurality of decoders. The extended transition activity measurement circuit comprises a plurality of extended transition activity measurement calculation circuit, and a majority extended transition activity measurement circuit connected to the plurality of extended transition activity measurement calculation circuits.
An eighth aspect of the present invention provides a signal encoding apparatus for a plurality of closely spaced signal lines, the apparatus comprising encoding means connected to the plurality of closely spaced signal lines, first multiplexing means connected to the plurality of encoding means to selectively switch between the encoding means, and extended transition activity measurement means connected to the first multiplexing means. The apparatus further comprises first signal inverting means connected to the extended transition activity measurement means, and first comparing means to connected to the first multiplexing means, the comparing means transmitting a signal to switch the first multiplexing means between the encoding means.
The apparatus of the present invention further provides a second signal inverting means connected to the output of the first signal inverting means, a plurality of decoding means connected to the first signal inverting means, and second multiplexing means connected to the plurality of decoding means. The extended transition activity measurement means comprises a plurality of extended transition activity measurement calculation means, and a majority extended transition activity measurement means connected to the plurality of extended transition activity measurement calculation means and outputting an inversion signal.
A ninth aspect of the present invention provides a signal encoding apparatus for a plurality of closely spaced signal lines, the apparatus comprising a plurality of encoders connected to the plurality of closely spaced signal lines, each encoder decomposing the plurality of closely spaced signal lines into a plurality of source windows, a first multiplexer connected to the plurality of encoders to selectively switch between the output of each encoder, and an extended transition activity measurement circuit connected to the first multiplexer that outputs an inversion signal. The apparatus further provides a first signal inverter connected to the extended transition activity measurement circuit, the first signal inverted receiving the inversion signal, and a first comparator to connected to the multiplexer, the comparator transmitting a signal to switch the multiplexer between the encoders.
The apparatus further provides a second signal inverter that receives the output of the first signal inverter and the inversion signal, a plurality of decoders connected to the second signal inverter, and a second multiplexer connected to the plurality of decoders. The second comparator outputs a switching signal to the second multiplexer based upon an executing task size.
The plurality of source windows in each encoder of the apparatus is cross-connected to target windows based upon the capacitance of the closely spaced signal lines. More specifically, the cross-connections between the source windows and the target windows in each decoder are such that target windows having signal lines with low signal transition activity are interposed between target windows with high signal transition activity. In the alternative, the cross-connections between the source windows and the target windows in each decoder are such that the two target windows having signal lines with highest signal transition activity are separated by the remaining target windows.
The apparatus further provides an extended transition activity measurement circuit comprising a plurality of extended transition activity measurement calculation circuits, and a majority extended transition activity measurement circuit connected to the plurality of extended transition activity measurement calculation circuits. The extended transition activity measurement circuit analyzes signal transitions on the closely spaced signal lines, and outputs the inversion signal based on the transition activity in the closely spaced signal lines.
The above aspects and advantages of the present invention will become apparent from the following detailed description and with reference to the accompanying drawing figures.